Difference between revisions of "Tutorials:Cadence:LayoutDRC"

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(Created page with "= Design Rule Check (DRC) = Our next step in the Design Process is to perform a Design Rule Check, more commonly known as DRC, on the layout. Although designers might be cons...")
 
 
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Our next step in the Design Process is to perform a Design Rule Check, more  commonly known as DRC, on the layout.  Although designers might be  conscious of the design rules when performing the layout, there is a possibility  of overlooking and thus violating the design rules.  So, the DRC is a step  taken to prompt us of any violations.  This step is important because the  violation of any design rules would result in a higher probability, and in some  cases an absolute certainty, that the fabricated chip does not work as desired.
 
Our next step in the Design Process is to perform a Design Rule Check, more  commonly known as DRC, on the layout.  Although designers might be  conscious of the design rules when performing the layout, there is a possibility  of overlooking and thus violating the design rules.  So, the DRC is a step  taken to prompt us of any violations.  This step is important because the  violation of any design rules would result in a higher probability, and in some  cases an absolute certainty, that the fabricated chip does not work as desired.
  
1. To run the DRC, choose DRC...  from the Verify menu in the layout view window.  A pop-up menu will appear.
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<ol>
 
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  <li><p>To run the DRC, choose DRC...  from the Verify menu in the layout view window.  A pop-up menu will appear.</p>
 
: [[File:Tutorials-Cadence-Layout_2.gif]]
 
: [[File:Tutorials-Cadence-Layout_2.gif]]
 
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<p>You need to make sure that you're in edit mode for your  layout that you want to run DRC on. For huge layouts, DRC might take a bit of  time to perform.  You can shorten  this time by deselecting the Echo Commands option.  Click on the OK  button.</p>
You need to make sure that you're in edit mode for your  layout that you want to run DRC on. For huge layouts, DRC might take a bit of  time to perform.  You can shorten  this time by deselecting the Echo Commands option.  Click on the OK  button.
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</li><br>
 
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  <li><p>Cadence then runs the DRC and reports the errors or  warnings, if any, in the ''CIW'' window.</p>
2. Cadence then runs the DRC and reports the errors or  warnings, if any, in the ''CIW'' window.
 
 
 
 
: [[File:Tutorials-Cadence-Layout_3.gif]]
 
: [[File:Tutorials-Cadence-Layout_3.gif]]
 
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<p>The CIW window above shows that there are no errors or warnings found in the  DRC process.</p>
The CIW window above shows that there are no errors or warnings found in the  DRC process.
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</li><br>
 
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  <li><p>Let's perform a DRC on a layout that has errors. For the purposes  of this tutorial, this step is strongly recommended so that you can gain some  experience in dealing with layout DRC violations.  You can purposely violate a design rule by stretching any of  the mask layers to some ridiculously large dimension or by moving/shifting some  layer as shown below. In this  case, the pactive and cc.dg contact layers are shifted slightly to the right.</p>
3. Let's perform a DRC on a layout that has errors. For the purposes  of this tutorial, this step is strongly recommended so that you can gain some  experience in dealing with layout DRC violations.  You can purposely violate a design rule by stretching any of  the mask layers to some ridiculously large dimension or by moving/shifting some  layer as shown below. In this  case, the pactive and cc.dg contact layers are shifted slightly to the right.
 
 
 
 
: [[File:Tutorials-Cadence-Drc_lab3.gif]]
 
: [[File:Tutorials-Cadence-Drc_lab3.gif]]
 
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<p>The layout above leads to the results of the DRC.  Errors are indicated  by markers (white as shown above)&nbsp;but in your layout, these markers will  blink.  The errors are also reported in the <em>CIW </em>as shown below.</p>
The layout above leads to the results of the DRC.  Errors are indicated  by markers (white as shown above)&nbsp;but in your layout, these markers will  blink.  The errors are also reported in the <em>CIW </em>as shown below.
 
 
 
 
: [[File:Tutorials-Cadence-Drc_lab4.gif]]
 
: [[File:Tutorials-Cadence-Drc_lab4.gif]]
 
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</li><br>
4. You may then proceed to correct the errors according to the design  rules. Taking the above as an example, SCMOS Rule 6.2 states that the minimum  spacing between active and contact layers is 0.90 um.
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  <li>You may then proceed to correct the errors according to the design  rules. Taking the above as an example, SCMOS Rule 6.2 states that the minimum  spacing between active and contact layers is 0.90 um.
 
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</li><br>
5. When performing huge layouts, the blinking markers might not be  easily located at times.  Fortunately, Cadence has an easy search  tool.  Under the Verify menu in the  layout window, choose Markers &rarr; Find...
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  <li><p>When performing huge layouts, the blinking markers might not be  easily located at times.  Fortunately, Cadence has an easy search  tool.  Under the Verify menu in the  layout window, choose Markers &rarr; Find...</p>
 
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<p>A pop-up menu will appear.  Click on the Zoom to Markers box.</p>
A pop-up menu will appear.  Click on the Zoom to Markers box.
 
 
 
 
: [[File:Tutorials-Cadence-Drc_lab5.gif]]
 
: [[File:Tutorials-Cadence-Drc_lab5.gif]]
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<p>Click on the Apply button  and Cadence will zoom in to the errors or warnings as desired.  If there are more than one  errors/warnings, as is almost always the case, you can view each one of them by  clicking on Next.</p>
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</li>
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</ol>
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<noinclude>
  
Click on the Apply button  and Cadence will zoom in to the errors or warnings as desired.  If there are more than one  errors/warnings, as is almost always the case, you can view each one of them by  clicking on Next.
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[[Tutorials:Cadence:CreatingLayoutInverter|Prev]] : [[Tutorials:Cadence:LayoutExtractingParasitics|Next]] : [[Tutorials:Cadence:Main|Up]]
  
  
 
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{{Template:CadenceDisclaimer}}
 
{{Template:CadenceDisclaimer}}
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</noinclude>

Latest revision as of 18:56, 10 November 2010

Design Rule Check (DRC)

Our next step in the Design Process is to perform a Design Rule Check, more commonly known as DRC, on the layout. Although designers might be conscious of the design rules when performing the layout, there is a possibility of overlooking and thus violating the design rules. So, the DRC is a step taken to prompt us of any violations. This step is important because the violation of any design rules would result in a higher probability, and in some cases an absolute certainty, that the fabricated chip does not work as desired.

  1. To run the DRC, choose DRC... from the Verify menu in the layout view window. A pop-up menu will appear.

    Tutorials-Cadence-Layout 2.gif

    You need to make sure that you're in edit mode for your layout that you want to run DRC on. For huge layouts, DRC might take a bit of time to perform. You can shorten this time by deselecting the Echo Commands option. Click on the OK button.


  2. Cadence then runs the DRC and reports the errors or warnings, if any, in the CIW window.

    Tutorials-Cadence-Layout 3.gif

    The CIW window above shows that there are no errors or warnings found in the DRC process.


  3. Let's perform a DRC on a layout that has errors. For the purposes of this tutorial, this step is strongly recommended so that you can gain some experience in dealing with layout DRC violations. You can purposely violate a design rule by stretching any of the mask layers to some ridiculously large dimension or by moving/shifting some layer as shown below. In this case, the pactive and cc.dg contact layers are shifted slightly to the right.

    Tutorials-Cadence-Drc lab3.gif

    The layout above leads to the results of the DRC. Errors are indicated by markers (white as shown above) but in your layout, these markers will blink. The errors are also reported in the CIW as shown below.

    Tutorials-Cadence-Drc lab4.gif

  4. You may then proceed to correct the errors according to the design rules. Taking the above as an example, SCMOS Rule 6.2 states that the minimum spacing between active and contact layers is 0.90 um.

  5. When performing huge layouts, the blinking markers might not be easily located at times. Fortunately, Cadence has an easy search tool. Under the Verify menu in the layout window, choose Markers → Find...

    A pop-up menu will appear. Click on the Zoom to Markers box.

    Tutorials-Cadence-Drc lab5.gif

    Click on the Apply button and Cadence will zoom in to the errors or warnings as desired. If there are more than one errors/warnings, as is almost always the case, you can view each one of them by clicking on Next.


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