Difference between revisions of "Tutorials:Cadence:Main"
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| − | This | + | This tutorial is also available as a [[Tutorials:Cadence:SinglePage | single wiki page]]. |
| − | + | {{:Tutorials:Cadence:Introduction}} | |
| − | + | = Table of Contents = | |
| − | + | * [[Tutorials:Cadence:ConventionsUsedInThisManual | Conventions used in this manual]] | |
| + | * [[Tutorials:Cadence:ConventionsUsedInThisManual | Login to the Linux server]] | ||
| + | * [[Tutorials:Cadence:StartingCadence | Starting Cadence]] | ||
| + | * [[Tutorials:Cadence:UsingLibraryManager | Using Library Manager]] | ||
| + | * [[Tutorials:Cadence:DesignHierarchy | Design Hierarchy]] | ||
| + | * [[Tutorials:Cadence:QuittingCadence | Quitting Cadence]] | ||
| + | * [[Tutorials:Cadence:CreatingNewLibrary | Creating a new library]] | ||
| + | * [[Tutorials:Cadence:CreatingSchematicTransistorIV | Creating Schematic: Transistor I-V]] | ||
| + | * [[Tutorials:Cadence:TransistorDCAnalysis | Transistor DC Analysis]] | ||
| + | * [[Tutorials:Cadence:CreatingSchematicInverter | Creating Schematic: Inverter]] | ||
| + | * [[Tutorials:Cadence:PrintSchematic | Printing Schematic]] | ||
| + | * [[Tutorials:Cadence:CreatingSymbolInverter | Creating Symbol: Inverter]] | ||
| + | * [[Tutorials:Cadence:SchematicSimulationDCAnalysis | Schematic simulation: DC Analysis]] | ||
| + | * [[Tutorials:Cadence:SchematicSimulationTransient | Schematic simulation: Transient]] | ||
| + | * [[Tutorials:Cadence:SchematicSimulationParametric | Schematic simulation: Parametric]] | ||
| + | * [[Tutorials:Cadence:CreatingLayoutInverter | Creating Layout: Inverter]] | ||
| + | * [[Tutorials:Cadence:LayoutDRC | Layout: Design Rule Check (DRC)]] | ||
| + | * [[Tutorials:Cadence:LayoutExtractingParasitics | Layout: Extracting Parasitics]] | ||
| + | * [[Tutorials:Cadence:LayoutLVS | Layout: Layout vs. Schematic (LVS)]] | ||
| + | * [[Tutorials:Cadence:LayoutSimulation | Layout simulation]] | ||
| + | * [[Tutorials:Cadence:VerilogHDL | Verilog HDL]] | ||
| + | * [[Tutorials:Cadence:CreatingBehavioralModel | Creating a behavioral model]] | ||
| + | * [[Tutorials:Cadence:VerilogSimulation | Verilog simulation]] | ||
| + | * [[Tutorials:Cadence:ExampleLayouts | Example layouts]] | ||
| + | * [[Tutorials:Cadence:AdvancedTopics | Advanced topics]] | ||
| + | * [[Tutorials:Cadence:Acknowledgment | Acknowledgment]] | ||
| + | |||
| + | |||
| + | ---- | ||
| + | {{Template:CadenceDisclaimer}} | ||
Latest revision as of 17:20, 29 January 2016
This tutorial is also available as a single wiki page.
Introduction
This manual is intended primarily for students in CSE463: Digital Integrated Circuits and Architecture offered at Washington University in St. Louis. Basic knowledge of how CMOS transistors operate is required. The main goal of this manual is to teach you to use the Cadence Design Environment to design and test digital CMOS circuits. The design toolkits are based on NCSU PDK 1.6 and Cadence IC 6.1 base.
This manual will walk you through all the necessary steps for designing and testing an inverter. First, we are going to create a schematic for the inverter. We, then, create a symbol for the inverter and test the transient and DC characteristics of this inverter using Analog Artist Simulator. Next, we are going to create a layout for the inverter and test the transient and DC characteristics on the layout of the inverter. Finally, we are going to create a behavioral view for the inverter in Verilog XL and simulate its behavior.
Use the following sections to guide yourself through the various design examples.
Table of Contents
- Conventions used in this manual
- Login to the Linux server
- Starting Cadence
- Using Library Manager
- Design Hierarchy
- Quitting Cadence
- Creating a new library
- Creating Schematic: Transistor I-V
- Transistor DC Analysis
- Creating Schematic: Inverter
- Printing Schematic
- Creating Symbol: Inverter
- Schematic simulation: DC Analysis
- Schematic simulation: Transient
- Schematic simulation: Parametric
- Creating Layout: Inverter
- Layout: Design Rule Check (DRC)
- Layout: Extracting Parasitics
- Layout: Layout vs. Schematic (LVS)
- Layout simulation
- Verilog HDL
- Creating a behavioral model
- Verilog simulation
- Example layouts
- Advanced topics
- Acknowledgment
Information is provided "as is" without warranty or guarantee of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise.
Please use this information at your own risk--and any attempt to use this information is at your own risk--we recommend using it on a copy of your data to be sure you understand what it does and under what conditions. Keep your master intact until you are personally satisfied with the use of this information within your environment."
Cadence® is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134
For web related questions contact: Viktor Gruev, Michael Hall
