Difference between revisions of "Tutorials:Cadence:Main"

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= Introduction =
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This tutorial is also available as a [[Tutorials:Cadence:SinglePage | single wiki page]].
  
This manual is intended primarily for students in ''CSE463: Digital Integrated Circuits and Architecture'' offered at Washington University in St. Louis. Basic knowledge of how CMOS transistors operate is required. The main goal of this manual is to teach you to use the Cadence Design Environment to design and test digital CMOS circuits. The design toolkits are based on NCSU PDK 1.6 and Cadence IC 6.1 base.
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{{:Tutorials:Cadence:Introduction}}
 
 
This manual will walk you through all the necessary steps for designing and testing an inverter. First, we are going to create a schematic for the inverter. We, then, create a symbol for the inverter and test the transient and DC characteristics of this inverter using Analog Artist Simulator. Next, we are going to create a layout for the inverter and test the transient and DC characteristics on the layout of the inverter. Finally, we are going to create a behavioral view for the inverter in Verilog XL and simulate its behavior.
 
 
 
Use the menu on the left to guide yourself through the various design examples.
 
 
 
Here is more information on [http://students.cec.wustl.edu/~tey1/cse463/CadenceInstall/ how to install Cadence].
 
  
 
= Table of Contents =
 
= Table of Contents =
  
 
* [[Tutorials:Cadence:ConventionsUsedInThisManual  | Conventions used in this manual]]
 
* [[Tutorials:Cadence:ConventionsUsedInThisManual  | Conventions used in this manual]]
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* [[Tutorials:Cadence:ConventionsUsedInThisManual  | Login to the Linux server]]
 
* [[Tutorials:Cadence:StartingCadence              | Starting Cadence]]
 
* [[Tutorials:Cadence:StartingCadence              | Starting Cadence]]
 
* [[Tutorials:Cadence:UsingLibraryManager          | Using Library Manager]]
 
* [[Tutorials:Cadence:UsingLibraryManager          | Using Library Manager]]
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* [[Tutorials:Cadence:SchematicSimulationDCAnalysis | Schematic simulation: DC Analysis]]
 
* [[Tutorials:Cadence:SchematicSimulationDCAnalysis | Schematic simulation: DC Analysis]]
 
* [[Tutorials:Cadence:SchematicSimulationTransient  | Schematic simulation: Transient]]
 
* [[Tutorials:Cadence:SchematicSimulationTransient  | Schematic simulation: Transient]]
* [[Tutorials:Cadence:SchematicSimualtionParametric | Schematic simulation: Parametric]]
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* [[Tutorials:Cadence:SchematicSimulationParametric | Schematic simulation: Parametric]]
 
* [[Tutorials:Cadence:CreatingLayoutInverter        | Creating Layout: Inverter]]
 
* [[Tutorials:Cadence:CreatingLayoutInverter        | Creating Layout: Inverter]]
 
* [[Tutorials:Cadence:LayoutDRC                    | Layout: Design Rule Check (DRC)]]
 
* [[Tutorials:Cadence:LayoutDRC                    | Layout: Design Rule Check (DRC)]]
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* [[Tutorials:Cadence:CreatingBehavioralModel      | Creating a behavioral model]]
 
* [[Tutorials:Cadence:CreatingBehavioralModel      | Creating a behavioral model]]
 
* [[Tutorials:Cadence:VerilogSimulation            | Verilog simulation]]
 
* [[Tutorials:Cadence:VerilogSimulation            | Verilog simulation]]
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* [[Tutorials:Cadence:ExampleLayouts                | Example layouts]]
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* [[Tutorials:Cadence:AdvancedTopics                | Advanced topics]]
 
* [[Tutorials:Cadence:Acknowledgment                | Acknowledgment]]
 
* [[Tutorials:Cadence:Acknowledgment                | Acknowledgment]]
  

Latest revision as of 17:20, 29 January 2016

This tutorial is also available as a single wiki page.

Introduction

This manual is intended primarily for students in CSE463: Digital Integrated Circuits and Architecture offered at Washington University in St. Louis. Basic knowledge of how CMOS transistors operate is required. The main goal of this manual is to teach you to use the Cadence Design Environment to design and test digital CMOS circuits. The design toolkits are based on NCSU PDK 1.6 and Cadence IC 6.1 base.

This manual will walk you through all the necessary steps for designing and testing an inverter. First, we are going to create a schematic for the inverter. We, then, create a symbol for the inverter and test the transient and DC characteristics of this inverter using Analog Artist Simulator. Next, we are going to create a layout for the inverter and test the transient and DC characteristics on the layout of the inverter. Finally, we are going to create a behavioral view for the inverter in Verilog XL and simulate its behavior.

Use the following sections to guide yourself through the various design examples.


Table of Contents



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