Difference between revisions of "Tutorials:Cadence:VerilogHDL"
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= Verilog Hardware Description Language = | = Verilog Hardware Description Language = | ||
| − | Verilog is a description language that describes the behavior of a logic circuit at gate level. | + | Verilog is a description language that describes the behavior of a logic circuit at gate level. It can also be used for simulation of a logic design. It does not just simulate the function of the circuit but also the delays for switching each gate. |
| − | The first step in running a Verilog simulation is to create the behavioral or functional model files for the circuit that | + | The first step in running a Verilog simulation is to create the behavioral or functional model files for the circuit that you wish to simulate. From the schematic file you can then run the simulation of the total design you have created. The last step is to evaluate the results from the input and output waveforms. |
| − | This section will enable you to create a Verilog file for your design (an example considered here is that of an inverter). | + | This section will enable you to create a Verilog file for your design (an example considered here is that of an inverter). You will also simulate this inverter using Cadence. |
| + | <noinclude> | ||
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| + | [[Tutorials:Cadence:LayoutSimulation|Prev]] : [[Tutorials:Cadence:CreatingBehavioralModel|Next]] : [[Tutorials:Cadence:Main|Up]] | ||
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{{Template:CadenceDisclaimer}} | {{Template:CadenceDisclaimer}} | ||
| + | </noinclude> | ||
Latest revision as of 18:58, 10 November 2010
Verilog Hardware Description Language
Verilog is a description language that describes the behavior of a logic circuit at gate level. It can also be used for simulation of a logic design. It does not just simulate the function of the circuit but also the delays for switching each gate.
The first step in running a Verilog simulation is to create the behavioral or functional model files for the circuit that you wish to simulate. From the schematic file you can then run the simulation of the total design you have created. The last step is to evaluate the results from the input and output waveforms.
This section will enable you to create a Verilog file for your design (an example considered here is that of an inverter). You will also simulate this inverter using Cadence.
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