Difference between revisions of "Tutorials:Cadence:VerilogHDL"
| (One intermediate revision by the same user not shown) | |||
| Line 6: | Line 6: | ||
This section will enable you to create a Verilog file for your design (an example considered here is that of an inverter). You will also simulate this inverter using Cadence. | This section will enable you to create a Verilog file for your design (an example considered here is that of an inverter). You will also simulate this inverter using Cadence. | ||
| + | <noinclude> | ||
| + | |||
| + | [[Tutorials:Cadence:LayoutSimulation|Prev]] : [[Tutorials:Cadence:CreatingBehavioralModel|Next]] : [[Tutorials:Cadence:Main|Up]] | ||
---- | ---- | ||
{{Template:CadenceDisclaimer}} | {{Template:CadenceDisclaimer}} | ||
| + | </noinclude> | ||
Latest revision as of 18:58, 10 November 2010
Verilog Hardware Description Language
Verilog is a description language that describes the behavior of a logic circuit at gate level. It can also be used for simulation of a logic design. It does not just simulate the function of the circuit but also the delays for switching each gate.
The first step in running a Verilog simulation is to create the behavioral or functional model files for the circuit that you wish to simulate. From the schematic file you can then run the simulation of the total design you have created. The last step is to evaluate the results from the input and output waveforms.
This section will enable you to create a Verilog file for your design (an example considered here is that of an inverter). You will also simulate this inverter using Cadence.
Information is provided "as is" without warranty or guarantee of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise.
Please use this information at your own risk--and any attempt to use this information is at your own risk--we recommend using it on a copy of your data to be sure you understand what it does and under what conditions. Keep your master intact until you are personally satisfied with the use of this information within your environment."
Cadence® is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134
For web related questions contact: Viktor Gruev, Michael Hall
