Difference between revisions of "Tutorials:Cadence:ExampleLayouts"

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= Example Layouts =
 
= Example Layouts =
  
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== Inverter ==
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 +
Here are several different ways to layout an inverter:
 +
 +
;Schematic
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:[[File:Tutorials-Cadence-ExLayout-Inv-Sch.png]]
 +
 +
 +
;Layout 1
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:[[File:Tutorials-Cadence-ExLayout-Inv-001.png]]
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:Area = 7.80um x 10.80um = 84.24um<sup>2</sup>
 +
 +
 +
;Layout 2
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:[[File:Tutorials-Cadence-ExLayout-Inv-003.png]]
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:Area = 7.80um x 13.20um = 102.96um<sup>2</sup>
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 +
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;Layout 3
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:[[File:Tutorials-Cadence-ExLayout-Inv-004.png]]
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:Area = 7.80um x 10.80um = 84.24um<sup>2</sup>
 +
 +
 +
;Layout 4
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:[[File:Tutorials-Cadence-ExLayout-Inv-005.png]]
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:Area = 7.20um x 16.20um = 116.64um<sup>2</sup>
 +
 +
This inverter layout is designed to abut to form a ring oscillator.  Notice the Metal 2 trace above the IN/OUT terminals.  This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator.  Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space.
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 +
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== Ring Oscillator ==
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Shown below is an 11-inverter ring oscillator:
 +
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;Schematic
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:[[File:Tutorials-Cadence-ExLayout-RO-001.png]]
 +
 +
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;Layout
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:[[File:Tutorials-Cadence-ExLayout-RO-002.png]]
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:Area = 55.20um x 16.20um = 894.24um<sup>2</sup>
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 +
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== 2-Input NAND Gate ==
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;Schematic
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:[[File:Tutorials-Cadence-ExLayout-nand2-Sch.png]]
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 +
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;Layout
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:[[File:Tutorials-Cadence-ExLayout-nand2-001.png]]
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:Area = 9.60um x 15.60um = 149.76um<sup>2</sup>
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 +
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== 2-Input NOR Gate ==
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;Schematic
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:[[File:Tutorials-Cadence-ExLayout-nor2-Sch.png]]
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 +
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;Layout
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:[[File:Tutorials-Cadence-ExLayout-nor2-001.png]]
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:Area = 8.70um x 17.10um = 148.77um<sup>2</sup>
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 +
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== Complex Function 1 ==
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Z = (AB+C)D
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Z = ((A' + B')C' + D')'
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;Schematic
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:[[File:Tutorials-Cadence-ExLayout-ComplexFunc1-Sch.png]]
 +
 +
 +
;Layout
 +
:[[File:Tutorials-Cadence-ExLayout-ComplexFunc1-001.png]]
 +
:Area = 14.40um x 18.60um = 267.84um<sup>2</sup>
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 +
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== Complex Function 2 ==
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Y = (A B'+C)G'+E F'
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Y = (((A'+B)C'+G)(E'+F))'
 +
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;Schematic
 +
:[[File:Tutorials-Cadence-ExLayout-ComplexFunc2-Sch.png]]
 +
 +
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;Layout
 +
:[[File:Tutorials-Cadence-ExLayout-ComplexFunc2-001.png]]
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:Area = 19.50um x 11.25um = 219.38um<sup>2</sup>
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 +
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== 2x1 Multiplexer ==
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;Schematic
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:[[File:Tutorials-Cadence-ExLayout-2x1MUX-Sch.png]]
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 +
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;Layout
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:[[File:Tutorials-Cadence-ExLayout-2x1MUX-001.png]]
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:Area = 14.40um x 13.80um = 198.72um<sup>2</sup>
 
<noinclude>
 
<noinclude>
  
−
[[Tutorials:Cadence:VerilogSimulation|Prev]] : [[Tutorials:Cadence:Acknowledgment|Next]] : [[Tutorials:Cadence:Main|Up]]
+
[[Tutorials:Cadence:VerilogSimulation|Prev]] : [[Tutorials:Cadence:AdvancedTopics|Next]] : [[Tutorials:Cadence:Main|Up]]
  
  

Latest revision as of 18:32, 16 November 2010

Example Layouts

Inverter

Here are several different ways to layout an inverter:

Schematic
Tutorials-Cadence-ExLayout-Inv-Sch.png


Layout 1
Tutorials-Cadence-ExLayout-Inv-001.png
Area = 7.80um x 10.80um = 84.24um2


Layout 2
Tutorials-Cadence-ExLayout-Inv-003.png
Area = 7.80um x 13.20um = 102.96um2


Layout 3
Tutorials-Cadence-ExLayout-Inv-004.png
Area = 7.80um x 10.80um = 84.24um2


Layout 4
Tutorials-Cadence-ExLayout-Inv-005.png
Area = 7.20um x 16.20um = 116.64um2

This inverter layout is designed to abut to form a ring oscillator. Notice the Metal 2 trace above the IN/OUT terminals. This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator. Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space.


Ring Oscillator

Shown below is an 11-inverter ring oscillator:

Schematic
Tutorials-Cadence-ExLayout-RO-001.png


Layout
Tutorials-Cadence-ExLayout-RO-002.png
Area = 55.20um x 16.20um = 894.24um2


2-Input NAND Gate

Schematic
Tutorials-Cadence-ExLayout-nand2-Sch.png


Layout
Tutorials-Cadence-ExLayout-nand2-001.png
Area = 9.60um x 15.60um = 149.76um2


2-Input NOR Gate

Schematic
Tutorials-Cadence-ExLayout-nor2-Sch.png


Layout
Tutorials-Cadence-ExLayout-nor2-001.png
Area = 8.70um x 17.10um = 148.77um2


Complex Function 1

Z = (AB+C)D

Z = ((A' + B')C' + D')'

Schematic
Tutorials-Cadence-ExLayout-ComplexFunc1-Sch.png


Layout
Tutorials-Cadence-ExLayout-ComplexFunc1-001.png
Area = 14.40um x 18.60um = 267.84um2


Complex Function 2

Y = (A B'+C)G'+E F'

Y = (((A'+B)C'+G)(E'+F))'

Schematic
Tutorials-Cadence-ExLayout-ComplexFunc2-Sch.png


Layout
Tutorials-Cadence-ExLayout-ComplexFunc2-001.png
Area = 19.50um x 11.25um = 219.38um2


2x1 Multiplexer

Schematic
Tutorials-Cadence-ExLayout-2x1MUX-Sch.png


Layout
Tutorials-Cadence-ExLayout-2x1MUX-001.png
Area = 14.40um x 13.80um = 198.72um2


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