Difference between revisions of "Tutorials:Cadence:Main"
| Line 11: | Line 11: | ||
= Table of Contents = | = Table of Contents = | ||
| − | * Conventions | + | * [[Tutorials:Cadence:ConventionsUsedInThisManual | Conventions used in this manual]] |
| − | * Starting Cadence | + | * [[Tutorials:Cadence:StartingCadence | Starting Cadence]] |
| − | * Using Library Manager | + | * [[Tutorials:Cadence:UsingLibraryManager | Using Library Manager]] |
| − | * Design Hierarchy | + | * [[Tutorials:Cadence:DesignHierarchy | Design Hierarchy]] |
| − | * Quitting Cadence | + | * [[Tutorials:Cadence:QuittingCadence | Quitting Cadence]] |
| − | * Creating a new library | + | * [[Tutorials:Cadence:CreatingNewLibrary | Creating a new library]] |
| − | * Creating Schematic: Transistor I-V | + | * [[Tutorials:Cadence:CreatingSchematicTransistorIV | Creating Schematic: Transistor I-V]] |
| − | * Transistor DC Analysis | + | * [[Tutorials:Cadence:TransistorDCAnalysis | Transistor DC Analysis]] |
| − | * Creating Schematic: Inverter | + | * [[Tutorials:Cadence:CreatingSchematicInverter | Creating Schematic: Inverter]] |
| − | * Printing Schematic | + | * [[Tutorials:Cadence:PrintSchematic | Printing Schematic]] |
| − | * Creating Symbol: Inverter | + | * [[Tutorials:Cadence:CreatingSymbolInverter | Creating Symbol: Inverter]] |
| − | * Schematic simulation: DC Analysis | + | * [[Tutorials:Cadence:SchematicSimulationDCAnalysis | Schematic simulation: DC Analysis]] |
| − | * Schematic simulation: Transient | + | * [[Tutorials:Cadence:SchematicSimulationTransient | Schematic simulation: Transient]] |
| − | * Schematic simulation: | + | * [[Tutorials:Cadence:SchematicSimualtionParametric | Schematic simulation: Parametric]] |
| − | * Creating Layout: Inverter | + | * [[Tutorials:Cadence:CreatingLayoutInverter | Creating Layout: Inverter]] |
| − | * Layout: Design Rule Check (DRC) | + | * [[Tutorials:Cadence:LayoutDRC | Layout: Design Rule Check (DRC)]] |
| − | * Layout: Extracting Parasitics | + | * [[Tutorials:Cadence:LayoutExtractingParasitics | Layout: Extracting Parasitics]] |
| − | * Layout: Layout vs. Schematic (LVS) | + | * [[Tutorials:Cadence:LayoutLVS | Layout: Layout vs. Schematic (LVS)]] |
| − | * Layout simulation | + | * [[Tutorials:Cadence:LayoutSimulation | Layout simulation]] |
| − | * Verilog HDL | + | * [[Tutorials:Cadence:VerilogHDL | Verilog HDL]] |
| − | * Creating a behavioral model | + | * [[Tutorials:Cadence:CreatingBehavioralModel | Creating a behavioral model]] |
| − | * Verilog simulation | + | * [[Tutorials:Cadence:VerilogSimulation | Verilog simulation]] |
| − | * Acknowledgment | + | * [[Tutorials:Cadence:Acknowledgment | Acknowledgment]] |
Revision as of 01:26, 29 October 2010
Introduction
This manual is intended primarily for students in CSE463: Digital Integrated Circuits and Architecture offered at Washington University at St. Louis. Basic knowledge of how CMOS transistors operate is required. The main goal of this manual is to teach you to use the Cadence Design Environment to design and test digital CMOS circuits. The design toolkits are based on NCSU PDK 1.6 and Cadence IC 6.1 base.
This manual will walk you through all the necessary steps for designing and testing an inverter. First, we are going to create a schematic for the inverter. We, then, create a symbol for the inverter and test the transient and DC characteristics of this inverter using Analog Artist Simulator. Next, we are going to create a layout for the inverter and test the transient and DC characteristics on the layout of the inverter. Finally, we are going to create a behavioral view for the inverter in Verilog XL and simulate its behavior.
Use the menu on the left to guide yourself through the various design examples.
Here is more information on how to install Cadence.
Table of Contents
- Conventions used in this manual
- Starting Cadence
- Using Library Manager
- Design Hierarchy
- Quitting Cadence
- Creating a new library
- Creating Schematic: Transistor I-V
- Transistor DC Analysis
- Creating Schematic: Inverter
- Printing Schematic
- Creating Symbol: Inverter
- Schematic simulation: DC Analysis
- Schematic simulation: Transient
- Schematic simulation: Parametric
- Creating Layout: Inverter
- Layout: Design Rule Check (DRC)
- Layout: Extracting Parasitics
- Layout: Layout vs. Schematic (LVS)
- Layout simulation
- Verilog HDL
- Creating a behavioral model
- Verilog simulation
- Acknowledgment
