Difference between revisions of "Tutorials:Cadence:ExampleLayouts"
| Line 41: | Line 41: | ||
;Layout | ;Layout | ||
:[[File:Tutorials-Cadence-ExLayout-RO-002.png]] | :[[File:Tutorials-Cadence-ExLayout-RO-002.png]] | ||
| − | :Area = 55.20um x 16. | + | :Area = 55.20um x 16.20um = 894.24um<sup>2</sup> |
| + | |||
| + | == 2-Input NAND Gate == | ||
| + | |||
| + | ;Schematic | ||
| + | :[[File:Tutorials-Cadence-ExLayout-nand2-Sch.png]] | ||
| + | |||
| + | |||
| + | ;Layout | ||
| + | :[[File:Tutorials-Cadence-ExLayout-nand2-001.png]] | ||
| + | :Area = 9.60um x 15.60um = 149.76um<sup>2</sup> | ||
| + | |||
| + | |||
| + | == 2-Input NOR Gate == | ||
| + | |||
| + | ;Schematic | ||
| + | :[[File:Tutorials-Cadence-ExLayout-nor2-Sch.png]] | ||
| + | |||
| + | |||
| + | ;Layout | ||
| + | :[[File:Tutorials-Cadence-ExLayout-nor2-001.png]] | ||
| + | :Area = 8.70um x 17.10um = 148.77um<sup>2</sup> | ||
<noinclude> | <noinclude> | ||
Revision as of 18:00, 16 November 2010
Contents
Example Layouts
Inverter
Here are several different ways to layout an inverter:
- Schematic
- Layout 1
- Area = 7.80um x 10.80um = 84.24um2
- Layout 2
- Area = 7.80um x 13.20um = 102.96um2
- Layout 3
- Area = 7.80um x 10.80um = 84.24um2
- Layout 4
- Area = 7.20um x 16.20um = 116.64um2
This inverter layout is designed to abut to form a ring oscillator. Notice the Metal 2 trace above the IN/OUT terminals. This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator. Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space.
Ring Oscillator
Shown below is an 11-inverter ring oscillator:
- Schematic
- Layout
- Area = 55.20um x 16.20um = 894.24um2
2-Input NAND Gate
- Schematic
- Layout
- Area = 9.60um x 15.60um = 149.76um2
2-Input NOR Gate
- Schematic
- Layout
- Area = 8.70um x 17.10um = 148.77um2
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