Difference between revisions of "Tutorials:Cadence:ExampleLayouts"
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This inverter layout is designed to abut to form a ring oscillator. Notice the Metal 2 trace above the IN/OUT terminals. This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator. Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space. | This inverter layout is designed to abut to form a ring oscillator. Notice the Metal 2 trace above the IN/OUT terminals. This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator. Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space. | ||
| + | |||
| + | == Ring Oscillator == | ||
| + | |||
| + | ;Schematic | ||
| + | :[[File:Tutorials-Cadence-ExLayout-RO-001.png]] | ||
| + | |||
| + | |||
| + | ;Layout | ||
| + | :[[File:Tutorials-Cadence-ExLayout-RO-002.png]] | ||
| + | :Area = 55.20um x 16.2um = 894.24um<sup>2</sup> | ||
<noinclude> | <noinclude> | ||
Revision as of 17:44, 16 November 2010
Example Layouts
Inverter
Shown below are several different ways to layout an inverter:
- Layout 1
- Area = 7.80um x 10.80um = 84.24um2
- Layout 2
- Area = 7.80um x 13.20um = 102.96um2
- Layout 3
- Area = 7.80um x 10.80um = 84.24um2
- Layout 4
- Area = 7.20um x 16.20um = 116.64um2
This inverter layout is designed to abut to form a ring oscillator. Notice the Metal 2 trace above the IN/OUT terminals. This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator. Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space.
Ring Oscillator
- Schematic
- Layout
- Area = 55.20um x 16.2um = 894.24um2
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