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Jump to navigationJump to search- 15:07, 2 November 2010 diff hist +5,342 N Tutorials:Cadence:LayoutLVS Created page with "= Layout: Layout vs. Schematic (LVS) = The next step is to perform LVS. Since we generated a layout with certain a W and L for the transistors (for the case discussed here, the..."
- 14:58, 2 November 2010 diff hist 0 N File:Tutorials-Cadence-Extracted 2.gif current
- 14:58, 2 November 2010 diff hist 0 N File:Tutorials-Cadence-Extracted 1.gif current
- 14:57, 2 November 2010 diff hist +1,799 N Tutorials:Cadence:LayoutExtractingParasitics Created page with "= Layout: Extracting Parasitics = A successful DRC ensures that the layout passes through the rules designed for faultless fabrication. However, it does not guarantee if it rea..."
- 21:29, 31 October 2010 diff hist -1,098 Tutorials:Cadence:CreatingLayoutInverter
- 21:28, 31 October 2010 diff hist +243 Tutorials:Cadence:CreatingLayoutInverter
- 21:15, 31 October 2010 diff hist +52 Tutorials:Cadence:LayoutDRC
- 21:10, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Layout 3.gif current
- 21:10, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Layout 2.gif current
- 21:09, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Drc lab5.gif current
- 21:09, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Drc lab4.gif current
- 21:09, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Drc lab3.gif current
- 21:08, 31 October 2010 diff hist +64 Tutorials:Cadence:LayoutDRC
- 21:04, 31 October 2010 diff hist +2,759 N Tutorials:Cadence:LayoutDRC Created page with "= Design Rule Check (DRC) = Our next step in the Design Process is to perform a Design Rule Check, more commonly known as DRC, on the layout. Although designers might be cons..."
- 20:54, 31 October 2010 diff hist +11 Tutorials:Cadence:CreatingLayoutInverter
- 20:46, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Lay 6.gif current
- 20:46, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Lay 5.gif current
- 20:46, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Lay 4.gif current
- 20:46, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Lay 3.gif current
- 20:45, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Lay 2.gif current
- 20:45, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Lay 1.gif current
- 20:28, 31 October 2010 diff hist +54 Tutorials:Cadence:CreatingLayoutInverter
- 20:26, 31 October 2010 diff hist +1,614 Tutorials:Cadence:CreatingLayoutInverter
- 20:15, 31 October 2010 diff hist -61 Tutorials:Cadence:CreatingLayoutInverter
- 20:11, 31 October 2010 diff hist +16,469 N Tutorials:Cadence:CreatingLayoutInverter Created page with "= Create Custom Layouts = By now, you would have known how to enter and simulate your designs using Spectre. The next step in the process of making an integrated circuit chip..."
- 19:49, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv Complete.gif current
- 19:49, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Parametric.gif current
- 19:49, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-ParametericTest fig4.gif current
- 19:49, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-ParametericTest fig3.gif current
- 19:49, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-ParametericTest fig2.gif current
- 19:49, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Inv schematic.gif current
- 19:49, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Add instanceNMOS.gif current
- 19:47, 31 October 2010 diff hist +4,655 N Tutorials:Cadence:SchematicSimulationParametric Created page with "= Parametric Analysis with Spectre = This tutorial will guide you through the process of performing a parametric analysis for the inverter circuit. In particular, we are going ..."
- 19:40, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv Transient7.gif current
- 19:40, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv Transient6.gif current
- 19:40, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv Transient5.gif current
- 19:40, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv Transient3.gif current
- 19:40, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv Transient1.gif current
- 19:39, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Sch test inv1.gif current
- 19:38, 31 October 2010 diff hist +2,113 N Tutorials:Cadence:SchematicSimulationTransient Created page with "= Schematic Simulation: Transient Analysis of The Inverter = Bring up the schematic of inv_test. We need to replace the dc voltage input source with a pulse source. Click on t..."
- 19:27, 31 October 2010 diff hist 0 Tutorials:Cadence:SchematicSimulationDCAnalysis
- 19:25, 31 October 2010 diff hist -110 Tutorials:Cadence:SchematicSimulationDCAnalysis
- 19:25, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Spectre DC4.gif current
- 19:25, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Spectre DC3.gif current
- 19:25, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Spectre DC2.gif current
- 19:24, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Spectre DC1.gif current
- 19:24, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv ComponentBrowser.gif current
- 19:24, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv AddInstanceVDD.gif current
- 19:24, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv AddInstanceCAP.gif current
- 19:24, 31 October 2010 diff hist 0 N File:Tutorials-Cadence-Schematic TestInv.gif current
