Tutorials:Cadence:CreatingBehavioralModel
Creating a Verilog Model for an Inverter
We'll now create a Verilog description of the inverter.
In your library manager click once on the CSE463 library and then click once on the inv cell view. Now left click Library manager: File → New → Cell view. In the dialog box type behavioral in the View field. Select Verilog for the Type. The New File window should look like the one bellow.
Left click OK. The text tool should now appear, with some basic template stuff inside. Anything preceded by a "//" is considered to be a comment.
An Emacs editor window will pop up. Add the following the statement in between the module statements:
not (out, in);
If the input and output names are not "in" and "out" for you, substitute them with your own names. The (out, in) syntax specifies the output and input for the inverter. In Verilog, the convention is that the output arguments of the module (gate) are listed before going on to the inputs.
This is all the text you need in order to describe your inverter. Now you can save the text file and close it. Cadence will tell you in the CIW whether the functional view is successfully parsed (no syntax errors) or not.
Now you are ready to simulate your Verilog code.
The commands that you used in the text file are describe bellow.
- module
- Defines the beginning of a Verilog module.
- inv(...)
- Specifies the name of the module. All pins (connections to the outside world) must be specified inside the parenthesis.
- in/out
- Defines what the input/output pins into the module are.
- not
- Tells that this gate is an inverter. There are three basic gates: AND, OR, NOT, NAND, and NOR.
- endmodule
- Signifies the end of this particular module.
The final model file should look like the one below:
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