Tutorials:Cadence:ExampleLayouts

Example Layouts

Inverter

Shown below are several different ways to layout an inverter:

Layout 1

Area = 7.80um x 10.80um = 84.24um²

Layout 2

Area = 7.80um x 13.20um = 102.96um²

Layout 3

Area = 7.80um x 10.80um = 84.24um²

Layout 4

Area = 7.20um x 16.20um = 116.64um²

This inverter layout is designed to abut to form a ring oscillator. Notice the Metal 2 trace above the IN/OUT terminals. This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator. Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space.

Ring Oscillator

Shown below is an 11-inverter ring oscillator:

Schematic

Layout

Area = 55.20um x 16.2um = 894.24um²

Prev : Next : Up

---

Information is provided "as is" without warranty or guarantee of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise.

Please use this information at your own risk--and any attempt to use this information is at your own risk--we recommend using it on a copy of your data to be sure you understand what it does and under what conditions. Keep your master intact until you are personally satisfied with the use of this information within your environment."

Cadence® is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134

For web related questions contact: Viktor Gruev, Michael Hall