Tutorials:Cadence:ExampleLayouts

Example Layouts

Inverter

Here are several different ways to layout an inverter:

Schematic

Layout 1

Area = 7.80um x 10.80um = 84.24um²

Layout 2

Area = 7.80um x 13.20um = 102.96um²

Layout 3

Area = 7.80um x 10.80um = 84.24um²

Layout 4

Area = 7.20um x 16.20um = 116.64um²

This inverter layout is designed to abut to form a ring oscillator. Notice the Metal 2 trace above the IN/OUT terminals. This provides the return path from the output of the last inverter to the input of the first inverter in the ring oscillator. Also, the bulk contacts are located above and below the PMOS and NMOS transistors so as to save horizontal space.

Ring Oscillator

Shown below is an 11-inverter ring oscillator:

Schematic

Layout

Area = 55.20um x 16.20um = 894.24um²

2-Input NAND Gate

Schematic

Layout

Area = 9.60um x 15.60um = 149.76um²

2-Input NOR Gate

Schematic

Layout

Area = 8.70um x 17.10um = 148.77um²

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